{"id":1574,"date":"2022-04-28T07:13:57","date_gmt":"2022-04-28T07:13:57","guid":{"rendered":"https:\/\/blog.amt.in\/?p=1574"},"modified":"2022-04-28T07:13:57","modified_gmt":"2022-04-28T07:13:57","slug":"introduction-to-multi-core-processor","status":"publish","type":"post","link":"https:\/\/blog.amt.in\/index.php\/2022\/04\/28\/introduction-to-multi-core-processor\/","title":{"rendered":"Introduction to Multi-core Processor"},"content":{"rendered":"

A\u00c2\u00a0multi-core processor\u00c2\u00a0is a\u00c2\u00a0computer processor\u00c2\u00a0integrated circuit\u00c2\u00a0with two or more separate\u00c2\u00a0processing units, called cores, each of which reads and executes\u00c2\u00a0program instructions, as if the computer had several processors.\u00c2\u00a0The instructions are ordinary\u00c2\u00a0CPU instructions\u00c2\u00a0(such as add, move data, and branch) but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support\u00c2\u00a0multithreading\u00c2\u00a0or other\u00c2\u00a0parallel computing\u00c2\u00a0techniques.\u00c2\u00a0Manufacturers typically integrate the cores onto a single integrated circuit\u00c2\u00a0die\u00c2\u00a0(known as a chip multiprocessor or CMP) or onto multiple dies in a single\u00c2\u00a0chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements\u00c2\u00a0multiprocessing\u00c2\u00a0in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share\u00c2\u00a0caches, and they may implement\u00c2\u00a0message passing\u00c2\u00a0or\u00c2\u00a0shared-memory\u00c2\u00a0inter-core communication methods. Common\u00c2\u00a0network topologies\u00c2\u00a0to interconnect cores include\u00c2\u00a0bus,\u00c2\u00a0ring, two-dimensional\u00c2\u00a0mesh, and\u00c2\u00a0crossbar. Homogeneous multi-core systems include only identical cores;\u00c2\u00a0heterogeneous\u00c2\u00a0multi-core systems have cores that are not identical (e.g.\u00c2\u00a0big.LITTLE\u00c2\u00a0have heterogeneous cores that share the same instruction set, while\u00c2\u00a0AMD Accelerated Processing Units\u00c2\u00a0have cores that don’t even share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as\u00c2\u00a0VLIW,\u00c2\u00a0superscalar,\u00c2\u00a0vector, or\u00c2\u00a0multithreading.<\/p>\n

Multi-core processors are widely used across many application domains, including\u00c2\u00a0general-purpose,\u00c2\u00a0embedded,\u00c2\u00a0network,\u00c2\u00a0digital signal processing\u00c2\u00a0(DSP), and\u00c2\u00a0graphics\u00c2\u00a0(GPU).<\/p>\n

The improvement in performance gained by the use of a multi-core processor depends very much on the\u00c2\u00a0software\u00c2\u00a0algorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that can\u00c2\u00a0run in parallel\u00c2\u00a0simultaneously on multiple cores; this effect is described by\u00c2\u00a0Amdahl’s law. In the best case, so-called\u00c2\u00a0embarrassingly parallel\u00c2\u00a0problems may realize speedup factors near the number of cores, or even more if the problem is split up enough to fit within each core’s cache(s), avoiding use of much slower main-system memory. Most applications, however, are not accelerated so much unless programmers invest a prohibitive amount of effort in re-factoring the whole problem.\u00c2\u00a0The parallelization of software is a significant ongoing topic of research.<\/p>\n

While manufacturing technology improves, reducing the size of individual gates, physical limits of\u00c2\u00a0semiconductor-based\u00c2\u00a0microelectronics\u00c2\u00a0have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some\u00c2\u00a0instruction-level parallelism\u00c2\u00a0(ILP) methods such as\u00c2\u00a0superscalar\u00c2\u00a0pipelining\u00c2\u00a0are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to\u00c2\u00a0thread-level parallelism\u00c2\u00a0(TLP) methods, and multiple independent CPUs are commonly used to increase a system’s overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs.<\/p>\n

Commercial incentives:<\/span><\/p>\n

Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit (IC), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for\u00c2\u00a0complex instruction set computing\u00c2\u00a0(CISC) architectures.\u00c2\u00a0Clock rates\u00c2\u00a0also increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s.<\/p>\n

As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example, Intel has produced a 48-core processor for research in cloud computing; each core has an\u00c2\u00a0x86\u00c2\u00a0architecture.<\/p>\n

Technical factors:<\/span><\/p>\n

Since computer manufacturers have long implemented\u00c2\u00a0symmetric multiprocessing\u00c2\u00a0(SMP) designs using discrete CPUs, the issues regarding implementing multi-core processor architecture and supporting it with software are well known.<\/p>\n

Additionally:<\/p>\n